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ltc2606/ltc2616/ltc2626 1 26061626fb typical application features applications description 16-/14-/12-bit rail-to-rail dacs with i 2 c interface the ltc ? 2606/ltc2616/ltc2626 are single 16-, 14- and 12-bit, 2.7v-to-5.5v rail-to-rail voltage output dacs in a 10-lead dfn package. they have built-in high performance output buffers and are guaranteed monotonic. these parts establish new board-density benchmarks for 16- and 14-bit dacs and advance performance standards for output drive and load regulation in single-supply, volt- age-output dacs. the parts use a 2-wire, i 2 c compatible serial interface. the ltc2606/ltc2616/ltc2626 operate in both the standard mode (clock rate of 100khz) and the fast mode (clock rate of 400khz). an asynchronous dac update pin ( ldac ) is also included. the ltc2606/ltc2616/ltc2626 incorporate a power-on reset circuit. during power-up, the voltage outputs rise less than 10mv above zero scale; and after power-up, they stay at zero scale until a valid write and update take place. the power-on reset circuit resets the ltc2606-1/ltc2616-1/ ltc2626-1 to mid-scale. the voltage outputs stay at mid- scale until a valid write and update take place. differential nonlinearity (ltc2606) n smallest pin-compatible single dacs: ltc2606: 16 bits ltc2616: 14 bits ltc2626: 12 bits n guaranteed 16-bit monotonic over temperature n 27 selectable addresses n 400khz i 2 c interface n wide 2.7v to 5.5v supply range n low power operation: 270a at 3v n power down to 1a, max n high rail-to-rail output drive ( 15ma, min) n double-buffered data latches n asynchronous dac update pin n ltc2606/ltc2616/ltc2626: power-on reset to zero scale n ltc2606-1/ltc2616-1/ltc2626-1: power-on reset to mid-scale n tiny (3mm 3mm) 10-lead dfn package n mobile communications n process control and industrial automation n instrumentation n automatic test equipment 7 10 4 5 1 dac register input register i 2 c interface 16-bit dac v out control logic i 2 c address decode ldac scl sda ca0 ca1 ca2 2606 bd 8 gnd 9 6 v cc ref 3 2 code 0 16384 32768 49152 65535 dnl (lsb) 2606 g02 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc2606/ltc2616/ltc2626 2 26061626fb pin configuration absolute maximum ratings any pin to gnd ............................................C 0.3v to 6v any pin to v cc ............................................ C6v to 0.3v maximum junction temperature...........................125c storage temperature range ...................C65c to 125c lead temperature (soldering, 10 sec) ..................300c operating temperature range: ltc2606c/ltc2616c/ltc2626c ltc2606-1c/ltc2616-1c/ltc2626-1c ...... 0c to 70c ltc2606i/ltc2616i/ltc2626i ltc2606-1i/ltc2616-1i/ltc2626-1i ......C 40c to 85c (note 1) top view 11 dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 ldac v cc gnd v out ref ca2 sda scl ca0 ca1 t jmax = 125c, ja = 43c/w exposed pad (pin 11) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking * package description temperature range ltc2606cdd#pbf ltc2606cdd#trpbf lajx 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2606idd#pbf ltc2606idd#trpbf lajx 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2606cdd-1#pbf ltc2606cdd-1#trpbf lajw 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2606idd-1#pbf ltc2606idd-1#trpbf lajw 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2616cdd#pbf ltc2616cdd#trpbf lbpq 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2616idd#pbf ltc2616idd#trpbf lbpq 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2616cdd-1#pbf ltc2626cdd-1#trpbf lbpr 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2616idd-1#pbf ltc2626idd-1#trpbf lbpr 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2626cdd#pbf ltc2626cdd#trpbf lbps 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2626idd#pbf ltc2626idd#trpbf lbps 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2626cdd-1#pbf ltc2626cdd-1#trpbf lbpt 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2626idd-1#pbf ltc2626idd-1#trpbf lbpt 10-lead (3mm 3mm) plastic dfn C40c to 85c lead free finish tape and reel part marking * package description temperature range ltc2606cdd ltc2606cdd#tr lajx 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2606idd ltc2606idd#tr lajx 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2606cdd-1 ltc2606cdd-1#tr lajw 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2606idd-1 ltc2606idd-1#tr lajw 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2616cdd ltc2616cdd#tr lbpq 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2616idd ltc2616idd#tr lbpq 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2616cdd-1 ltc2616cdd-1#tr lbpr 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2616idd-1 ltc2616idd-1#tr lbpr 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2626cdd ltc2626cdd#tr lbps 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2626idd ltc2626idd#tr lbps 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2626cdd-1 ltc2626cdd-1#tr lbpt 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2626idd-1 ltc2626idd-1#tr lbpt 10-lead (3mm 3mm) plastic dfn C40c to 85c
ltc2606/ltc2616/ltc2626 3 26061626fb electrical characteristics the denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.7v), v out unloaded, unless otherwise noted. ltc2626/ltc2626-1 ltc2616/ltc2616-1 ltc2606/ltc2606-1 symbol parameter conditions min typ max min typ max min typ max units dc performance resolution 12 14 16 bits monotonicity (note 2) 12 14 16 bits dnl differential nonlinearity (note 2) 0.5 1 1 lsb inl integral nonlinearity (note 2) 1 4 4 16 14 64 lsb load regulation v ref = v cc = 5v, mid-scale i out = 0ma to 15ma sourcing i out = 0ma to 15ma sinking 0.025 0.05 0.125 0.125 0.1 0.2 0.5 0.5 0.5 0.7 2 2 lsb/ma lsb/ma v ref = v cc = 2.7v, mid-scale i out = 0ma to 7.5ma sourcing i out = 0ma to 7.5ma sinking 0.05 0.1 0.25 0.25 0.2 0.4 1 1 0.9 1.5 4 4 lsb/ma lsb/ma zse zero-scale error code = 0 19 19 19 mv v os offset error (note 5) 1 9 1 9 1 9 mv v os temperature coef? cient 5 5 5 v/c ge gain error 0.1 0.7 0.1 0.7 0.1 0.7 %fsr gain temperature coef? cient 8.5 8.5 8.5 ppm/c
ltc2606/ltc2616/ltc2626 4 26061626fb electrical characteristics the denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.7v), v out unloaded, unless otherwise noted. (note 11) symbol parameter conditions min typ max units psr power supply rejection v cc = 10% C81 db r out dc output impedance v ref = v cc = 5v, mid-scale; C15ma i out 15ma v ref = v cc = 2.7v, mid-scale; C7.5ma i out 0.05 0.06 0.15 0.15 i sc short-circuit output current v cc = 5.5v, v ref = 5.5v code: zero-scale; forcing output to v cc code: full-scale; forcing output to gnd 15 15 34 36 60 60 ma ma v cc = 2.7v, v ref = 2.7v code: zero-scale; forcing output to v cc code: full-scale; forcing output to gnd 7.5 7.5 22 29 50 50 ma ma reference input input voltage range 0v cc v resistance normal mode 88 124 160 k capacitance 15 pf i ref reference current, power down mode dac powered down 0.001 1 a power supply v cc positive supply voltage for speci? ed performance 2.7 5.5 v i cc supply current v cc = 5v (note 3) v cc = 3v (note 3) dac powered down (note 3) v cc = 5v dac powered down (note 3) v cc = 3v 0.340 0.27 0.35 0.10 0.5 0.4 1 1 ma ma a a digital i/o (note 11) v il low level input voltage (sda and scl) C0.5 0.3v cc v v ih high level input voltage (sda and scl) (note 8) 0.7v cc v v il( ldac ) low level input voltage ( ldac )v cc = 4.5v to 5.5v v cc = 2.7v to 5.5v 0.8 0.6 v v v ih( ldac ) high level input voltage ( ldac )v cc = 2.7v to 5.5v v cc = 2.7v to 3.6v 2.4 2.0 v v v il(ca n ) low level input voltage on ca n ( n = 0, 1, 2) see test circuit 1 0.15v cc v v ih(ca n ) high level input voltage on ca n ( n = 0, 1, 2) see test circuit 1 0.85v cc v r inh resistance from ca n ( n = 0, 1, 2) to v cc to set ca n = v cc see test circuit 2 10 k r inl resistance from ca n ( n = 0, 1, 2) to gnd to set ca n = gnd see test circuit 2 10 k r inf resistance from ca n ( n = 0, 1, 2) to v cc or gnd to set ca n = float see test circuit 2 2m v ol low level output voltage sink current = 3ma 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 9) 20 + 0.1c b 250 ns t sp pulse width of spikes suppressed by input filter 050ns i in input leakage 0.1v cc v in 0.9v cc 1a c in i/o pin capacitance (note 4) 10 pf c b capacitive load for each bus line 400 pf c cax external capacitive load on address pins ca n ( n = 0, 1, 2) 10 pf
ltc2606/ltc2616/ltc2626 5 26061626fb timing characteristics symbol parameter conditions min typ max units v cc = 2.7v to 5.5v f scl scl clock frequency 0 400 khz t hd(sta) hold time (repeated) start condition 0.6 s t low low period of the scl clock pin 1.3 s t high high period of the scl clock pin 0.6 s t su(sta) set-up time for a repeated start condition 0.6 s t hd(dat) data hold time 0 0.9 s t su(dat) data set-up time 100 ns t r rise time of both sda and scl signals (note 9) 20 + 0.1c b 300 ns t f fall time of both sda and scl signals (note 9) 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition 0.6 s t buf bus free time between a stop and start condition 1.3 s t 1 falling edge of 9th clock of the 3rd input byte to ldac high or low transition 400 ns t 2 ldac low pulse width 20 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: linearity and monotonicity are de? ned from code k l to code 2 n C 1, where n is the resolution and k l is given by k l = 0.016(2 n /v ref ), rounded to the nearest whole code. for v ref = 4.096v and n = 16, k l = 256 and linearity is de? ned from code 256 to code 65,535. note 3: digital inputs at 0v or v cc . note 4: guaranteed by design and not production tested. note 5: inferred from measurement at code 256 (ltc2606/ltc2606-1), code 64 (ltc2616/ltc2616-1) or code 16 (ltc2626/ltc2626-1) and at full-scale. note 6: v cc = 5v, v ref = 4.096v. dac is stepped 1/4-scale to 3/4-scale and 3/4-scale to 1/4-scale. load is 2k in parallel with 200pf to gnd. note 7: v cc = 5v, v ref = 4.096v. dac is stepped 1lsb between half scale and half scale C 1. load is 2k in parallel with 200pf to gnd. note 8: maximum v ih = v cc(max) + 0.5v note 9: c b = capacitance of one bus line in pf. note 10: all values refer to v ih(min) and v il(max) levels. note 11: these speci? cations apply to ltc2606/ltc2606-1, ltc2616/ ltc2616-1, ltc2626/ltc2626-1. the denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (see figure 1) (notes 10, 11) electrical characteristics the denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.7v), v out unloaded, unless otherwise noted. ltc2626/ltc2626-1 ltc2616/ltc2616-1 ltc2606/ltc2606-1 symbol parameter conditions min typ max min typ max min typ max units ac performance t s settling time (note 6) 0.024% (1lsb at 12 bits) 0.006% (1lsb at 14 bits) 0.0015% (1lsb at 16 bits) 77 9 7 9 10 s s s settling time for 1lsb step (note 7) 0.024% (1lsb at 12 bits) 0.006% (1lsb at 14 bits) 0.0015% (1lsb at 16 bits) 2.7 2.7 4.8 2.7 4.8 5.2 s s s voltage output slew rate 0.75 0.75 0.75 v/s capacitive load driving 1000 1000 1000 pf glitch impulse at mid-scale transition 12 12 12 nv?s multiplying bandwidth 180 180 180 khz e n output voltage noise density at f = 1khz at f = 10khz 120 100 120 100 120 100 nv/ hz nv/ hz output voltage noise 0.1hz to 10hz 15 15 15 v p-p
ltc2606/ltc2616/ltc2626 6 26061626fb typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature dnl vs temperature inl vs v ref dnl vs v ref settling to 1lsb settling of full-scale step ltc2606 code 0 16384 32768 49152 65535 inl (lsb) 2606 g01 32 24 16 8 0 C8 C16 C24 C32 v cc = 5v v ref = 4.096v code 0 16384 32768 49152 65535 dnl (lsb) 2606 g02 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v temperature ( c) C50 C30 C10 10 30 50 70 90 inl (lsb) 2606 g03 32 24 16 8 0 C8 C16 C24 C32 v cc = 5v v ref = 4.096v inl (pos) inl (neg) temperature ( c) C50 C30 C10 10 30 50 70 90 dnl (lsb) 2606 g04 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v dnl (pos) dnl (neg) v ref (v) 0 1 2 3 4 5 inl (lsb) 2606 g05 32 24 16 8 0 C8 C16 C24 C32 v cc = 5.5v inl (pos) inl (neg) v ref (v) 0 1 2 3 4 5 dnl (lsb) 2606 g06 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 v cc = 5.5v dnl (pos) dnl (neg) 2 s/div 2606 g07 v out 100 v/div scl 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 9.7 s 9th clock of 3rd data byte 5 s/div 2606 g08 v out 100 v/div scr 2v/div settling to 1lsb v cc = 5v, v ref = 4.096v code 512 to 65535 step average of 2048 events 12.3 s 9th clock of 3rd data byte
ltc2606/ltc2616/ltc2626 7 26061626fb typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) settling to 1lsb integral nonlinearity (inl) differential nonlinearity (dnl) settling to 1lsb current limiting load regulation offset error vs temperature ltc2616 ltc2626 ltc2606/ltc2616/ltc2626 code 0 4096 8192 12288 16383 inl (lsb) 2606 g09 8 6 4 2 0 C2 C4 C6 C8 v cc = 5v v ref = 4.096v code 0 4096 8192 12288 16383 dnl (lsb) 2606 g10 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v 2 s/div 2606 g11 v out 100 v/div scl 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 8.9 s 9th clock of 3rd data byte code 0 1024 2048 3072 4095 inl (lsb) 2606 g12 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 v cc = 5v v ref = 4.096v code 0 1024 2048 3072 4095 dnl (lsb) 2606 g13 v cc = 5v v ref = 4.096v 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 2 s/div 2606 g14 v out 1mv/div scl 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 6.8 s 9th clock of 3rd data byte i out (ma) C40 C30 C20 C10 0 10 20 30 40 v out (v) 2606 g17 0.10 0.08 0.06 0.04 0.02 0 C0.02 C0.04 C0.06 C0.08 C0.10 v ref = v cc = 5v v ref = v cc = 3v v ref = v cc = 5v v ref = v cc = 3v code = midscale i out (ma) C35 C25 C15 C5 5 15 25 35 v out (mv) 2606 g18 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v ref = v cc = 5v code = midscale v ref = v cc = 3v temperature ( c) C50 C30 C10 10 30 50 70 90 offset error (mv) 2606 g19 3 2 1 0 C1 C2 C3
ltc2606/ltc2616/ltc2626 8 26061626fb typical performance characteristics zero-scale error vs temperature gain error vs temperature offset error vs v cc gain error vs v cc i cc shutdown vs v cc large-signal response mid-scale glitch impulse power-on reset glitch headroom at rails vs output current ltc2606/ltc2616/ltc2626 temperature ( c) C50 C30 C10 10 30 50 70 90 zero-scale error (mv) 2606 g20 3 2.5 2.0 1.5 1.0 0.5 0 temperature ( c) C50 C30 C10 10 30 50 70 90 gain error (%fsr) 2606 g21 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 offset error (mv) 2606 g22 3 2 1 0 C1 C2 C3 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 gain error (%fsr) 2606 g23 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 i cc (na) 2606 g24 450 400 350 300 250 200 150 100 50 0 2.5 s/div v out 0.5v/div 2606 g25 v ref = v cc = 5v 1/4-scale to 3/4-scale v out 10mv/div scl 2v/div 2.5 s/div 2606 g26 transition from ms-1 to ms transition from ms to ms-1 9th clock of 3rd data byte v out 10mv/div 250 s/div 2606 g27 v cc 1v/div 4mv peak i out (ma) 0 1 2 3 4 5 6 7 8 910 v out (v) 2606 g28 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5v sourcing 3v sourcing 3v sinking 5v sinking
ltc2606/ltc2616/ltc2626 9 26061626fb typical performance characteristics power-on reset to mid-scale supply current vs logic voltage supply current vs logic voltage multiplying bandwidth output voltage noise, 0.1hz to 10hz short-circuit output current vs v out (sinking) short-circuit output current vs v out (sourcing) ltc2606/ltc2616/ltc2626 1v/div 500 s/div 2606 g29 v cc v out v ref = v cc logic voltage (v) 0 i cc ( a) 650 600 550 500 450 400 350 300 C 250 4 2606 g30 123 5 3.5 0.5 1.5 2.5 4.5 v cc = 5v sweep ldac 0v to v cc logic voltage (v) 0 i cc ( a) 0.8 1.0 1.2 4 2606 g31 0.6 0.4 0.7 0.9 1.1 0.5 0.3 0.2 1 0.5 2 1.5 3 3.5 4.5 2.5 5 hysteresis 370mv v cc = 5v sweep scl and sda 0v to v cc and v cc to 0v frequency (hz) 1k db 0 C3 C6 C9 C12 C15 C18 C21 C24 C27 C30 C33 C36 1m 2606 g32 10k 100k v cc = 5v v ref (dc) = 2v v ref (ac) = 0.2v p-p code = full scale v out 10 v/div seconds 012345678910 2606 g33 1v/div 10ma/div 0ma 2606 g18 v cc = 5.5v v ref = 5.6v code = 0 v out swept 0v to v cc 1v/div 10ma/div 0ma 2606 g19 v cc = 5.5v v ref = 5.6v code = full scale v out swept v cc to 0v
ltc2606/ltc2616/ltc2626 10 26061626fb pin functions ca2 (pin 1): chip address bit 2. tie this pin to v cc , gnd or leave it ? oating to select an i 2 c slave address for the part (table 1). sda (pin 2): serial data bidirectional pin. data is shifted into the sda pin and acknowledged by the sda pin. this pin is high impedance while data is shifted in. open-drain n-channel output during acknowledgment. sda requires a pull-up resistor or current source to v cc . scl (pin 3): serial clock input pin. data is shifted into the sda pin at the rising edges of the clock. this high impedance pin requires a pull-up resistor or current source to v cc . ca0 (pin 4): chip address bit 0. tie this pin to v cc , gnd or leave it ? oating to select an i 2 c slave address for the part (table 1). ca1 (pin 5): chip address bit 1. tie this pin to v cc , gnd or leave it ? oating to select an i 2 c slave address for the part (table 1). ref (pin 6): reference voltage input. 0v v ref v cc . v out (pin 7): dac analog voltage output. the output range is 0v to v ref . gnd (pin 8): analog ground. v cc (pin 9): supply voltage input. 2.7v v cc 5.5v. ldac (pin 10): asynchronous dac update. a falling edge on this input after four bytes have been written into the part immediately updates the dac register with the contents of the input register. a low on this input without a complete 32-bit (four bytes including the slave address) data write transfer to the part does not update the dac output. soft- ware power-down is disabled when ldac is low. exposed pad (pin 11): ground. must be soldered to pcb ground.
ltc2606/ltc2616/ltc2626 11 26061626fb block diagram test circuits 7 10 4 5 1 dac register input register i 2 c interface 16-bit dac v out control logic i 2 c address decode ldac scl sda ca0 ca1 ca2 2606 bd 8 gnd 9 6 v cc ref 3 2 100 r inh /r inl /r inf v ih(ca n ) /v il(ca n ) ca n gnd 2606 tc v dd test circuit 2 test circuit 1 ca n
ltc2606/ltc2616/ltc2626 12 26061626fb timing diagrams figure 1 figure 2b figure 2a sda t f s t r t low t hd(sta) all voltage levels refer to v ih(min) and v il(max) levels t hd(dat) t su(dat) t su(sta) t hd(sta) t su(sto) t sp t buf t r t f t high scl s p s 2606 f01 ack ack 123456789123456789123456789123456789 2606 f02a ack t 1 start sda a6 a5 a4 a3 slave address a2 a1 a0 scl ldac c2 c3 c1 c0 x x x x ack 1st data byte 2nd data byte 3rd data byte t 2 9th clock of 3rd data byte t 1 scl ldac 2606 f02b
ltc2606/ltc2616/ltc2626 13 26061626fb operation power-on reset the ltc2606/ltc2616/ltc2626 clear the outputs to zero-scale when power is ? rst applied, making system initialization consistent and repeatable. the ltc2606-1/ ltc2616-1/ltc2626-1 set the voltage outputs to mid-scale when power is ? rst applied. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2606/ ltc2616/ltc2626 contain circuitry to reduce the power- on glitch; furthermore, the glitch amplitude can be made arbitrarily small by reducing the ramp rate of the power supply. for example, if the power supply is ramped to 5v in 1ms, the analog outputs rise less than 10mv above ground (typ) during power-on. see power-on reset glitch in the typical performance characteristics section. power supply sequencing the voltage at ref (pin 6) should be kept within the range C 0.3v v ref v cc + 0.3v (see absolute maximum rat- ings). particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at v cc (pin 9) is in transition. transfer function the digital-to-analog transfer function is: v out(ideal) = k 2 n ? ? ? ? ? ? v ref where k is the decimal equivalent of the binary dac input code, n is the resolution and v ref is the voltage at ref (pin 6). serial digital interface the ltc2606/ltc2616/ltc2626 communicate with a host using the standard 2-wire i 2 c interface. the timing diagrams (figures 1 and 2) show the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the value of these pull-up resistors is dependent on the power supply and can be obtained from the i 2 c speci? cations. for an i 2 c bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pf. the v cc power should not be removed from the ltc2606/ltc2616/ltc2626 when the i 2 c bus is active to avoid loading the i 2 c bus lines through the internal esd protection diodes. the ltc2606/ltc2616/ltc2626 are receive-only (slave) devices. the master can write to the ltc2606/ltc2616/ ltc2626. the ltc2606/ltc2616/ltc2626 do not respond to a read from the master. the start (s) and stop (p) conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a communica- tion to a slave device by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. when the master has ? nished communicating with the slave, it issues a stop condition. a stop condition is generated by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. acknowledge the acknowledge signal is used for handshaking between the master and the slave. an acknowledge (active low) generated by the slave lets the master know that the lat- est byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line (high) during the acknowledge clock pulse. the slave-receiver must pull down the sda bus line during the acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. the ltc2606/ltc2616/ltc2626 respond to a write by a master in this manner. the ltc2606/ltc2616/ltc2626 do not acknowledge a read (retains sda high during the period of the acknowledge clock pulse).
ltc2606/ltc2616/ltc2626 14 26061626fb operation chip address the state of ca0, ca1 and ca2 decides the slave address of the part. the pins ca0, ca1 and ca2 can be each set to any one of three states: v cc , gnd or ? oat. this results in 27 selectable addresses for the part. the slave address assignments are shown in table 1. table 1. slave address map ca2 ca1 ca0 a6 a5 a4 a3 a2 a1 a0 gnd gnd gnd 0 0 1 0 0 0 0 gnd gnd float 0 0 1 0 0 0 1 gnd gnd v cc 00100 10 gnd float gnd 0 0 1 0 0 1 1 gnd float float 0 1 0 0 0 0 0 gnd float v cc 01000 01 gnd v cc gnd 0 1 0 0 0 1 0 gnd v cc float 0 1 0 0 0 1 1 gnd v cc v cc 01100 00 float gnd gnd 0 1 1 0 0 0 1 float gnd float 0 1 1 0 0 1 0 float gnd v cc 01100 11 float float gnd 1 0 0 0 0 0 0 float float float 1 0 0 0 0 0 1 float float v cc 10000 10 float v cc gnd 1 0 0 0 0 1 1 float v cc float 1 0 1 0 0 0 0 float v cc v cc 10100 01 v cc gnd gnd 1 0 1 0 0 1 0 v cc gnd float 1 0 1 0 0 1 1 v cc gnd v cc 11000 00 v cc float gnd 1 1 0 0 0 0 1 v cc float float 1 1 0 0 0 1 0 v cc float v cc 11000 11 v cc v cc gnd 1 1 1 0 0 0 0 v cc v cc float 1 1 1 0 0 0 1 v cc v cc v cc 11100 10 global address 1 1 1 0 0 1 1 in addition to the address selected by the address pins, the parts also respond to a global address. this address allows a common write to all ltc2606, ltc2616 and ltc2626 parts to be accomplished with one 3-byte write transaction on the i 2 c bus. the global address is a 7-bit on-chip hardwired address and is not selectable by ca0, ca1 and ca2. the addresses corresponding to the states of ca0, ca1 and ca2 and the global address are shown in table 1. the maximum capacitive load allowed on the address pins (ca0, ca1 and ca2) is 10pf, as these pins are driven during address detection to determine if they are ? oating. write word protocol the master initiates communication with the ltc2606/ ltc2616/ltc2626 with a start condition and a 7-bit slave address followed by the write bit (w) = 0. the ltc2606/ ltc2616/ltc2626 acknowledges by pulling the sda pin low at the 9th clock if the 7-bit slave address matches the address of the parts (set by ca0, ca1 and ca2) or the global address. the master then transmits three bytes of data. the ltc2606/ltc2616/ltc2626 acknowledges each byte of data by pulling the sda line low at the 9th clock of each data byte transmission. after receiving three complete bytes of data, the ltc2606/ltc2616/ltc2626 executes the command speci? ed in the 24-bit input word. if more than three data bytes are transmitted after a valid 7-bit slave address, the ltc2606/ltc2616/ltc2626 do not acknowledge the extra bytes of data (sda is high during the 9th clock). the format of the three data bytes is shown in figure 3. the ? rst byte of the input word consists of the 4-bit com- mand and four dont care bits. the next two bytes consist of the 16-bit data word. the 16-bit data word consists of the 16-, 14- or 12-bit input code, msb to lsb, followed by 0, 2 or 4 dont care bits (ltc2606, ltc2616 and ltc2626 respectively). a typical ltc2606 write transaction is shown in figure 4. the command assignments (c3-c0) are shown in table 2. the ? rst four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32-bit shift register into the input register. in an update operation, the data word is copied from the input register to the dac register and converted to an analog voltage at the dac output. the update operation also powers up the dac if it had been in power-down mode. the data path and registers are shown in the block diagram.
ltc2606/ltc2616/ltc2626 15 26061626fb operation power-down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever the dac output is not needed. when in power-down, the buffer ampli? er, bias circuit and reference input is disabled and draws essentially zero current. the dac output is put into a high impedance state, and the output pin is passively pulled to ground through 90k resistors. input- and dac-register contents are not disturbed during power-down. table 2 command * c3 c2 c1 c0 0 0 0 0 write to input register 0 0 0 1 update (power up) dac register 0 0 1 1 write to and update (power up) 0 1 0 0 power down 1 1 1 1 no operation *command codes not shown are reserved and should not be used. the dac channel can be put into power-down mode by using command 0100 b . the 16-bit data word is ignored. the supply and reference currents are reduced to almost zero when the dac is powered down; the effective resis- tance at ref becomes a high impedance input (typically >1g). normal operation can be resumed by executing any com- mand which includes a dac update, as shown in table 2 or performing an asychronous update ( ldac ) as described in the next section. the dac is powered up as its voltage output is updated. when the dac in powered-down state is powered up and updated, normal settling is delayed. the main bias generation circuit block has been automatically shut down in addition to the dac ampli? er and reference input and so the power-up delay time is: 12s (for v cc = 5v) or 30s (for v cc = 3v) asynchronous dac update using ldac in addition to the update commands shown in table 2, the ldac pin asynchronously updates the dac register with the contents of the input register. asynchronous update is disabled when the input word is being clocked into the part. if a complete input word has been written to the part, a low on the ldac pin causes the dac register to be updated with the contents of the input register. if the input word is being written to the part, a low going pulse on the ldac pin before the completion of three bytes of data powers up the dac but does not cause the output to be updated. if ldac remains low after a complete input word has been written to the part, then ldac is recognized, the command speci? ed in the 24-bit word just transferred is executed and the dac output is updated. figure 3 c3 1st data byte input word (ltc2606) write word protocol for ltc2606/ltc2616/ltc1626 c2 c1 c0 x x x x d13 d14 d15 s wa slave address 1st data byte d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a 2nd data byte a 3rd data byte a p 2606 f03 2nd data byte input word 3rd data byte c3 1st data byte input word (ltc2616) c2 c1 c0 x x x x d11 d12 d13 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x 2nd data byte 3rd data byte c3 1st data byte input word (ltc2626) c2 c1 c0 x x x x d9 d10 d11 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x 2nd data byte 3rd data byte
ltc2606/ltc2616/ltc2626 16 26061626fb operation the dac is powered up when ldac is taken low, inde- pendent of any activity on the i 2 c bus. if ldac is low at the falling edge of the 9th clock of the 3rd byte of data, it inhibits any software power-down command that was speci? ed in the input word. voltage output the rail-to-rail ampli? er has guaranteed load regulation when sourcing or sinking up to 15ma at 5v (7.5ma at 3v). load regulation is a measure of the ampli? ers ability to maintain the rated voltage accuracy over a wide range of load conditions. the measured change in output voltage per milliampere of forced load current change is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the ampli? ers dc output impedance is 0.050 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25 typical channel resistance of the output devices; e.g., when sinking 1ma, the minimum output voltage = 25 ? 1ma = 25mv. see the graph headroom at rails vs output current in the typical performance charac- teristics section. the ampli? er is stable driving capacitive loads of up to 1000pf. board layout the excellent load regulation performance is achieved in part by keeping signal and power grounds separated internally and by reducing shared internal resistance. the gnd pin functions both as the node to which the refer- ence and output voltages are referred and as a return path for power currents in the device. because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. the pc board should have separate areas for the analog and digital sections of the circuit. this keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the devices ground pin as possible. ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. the gnd pin of the part should be connected to analog ground. resistance from the gnd pin to system star ground should be as low as possible. resistance here will add directly to the effective dc output impedance of the device (typically 0.050). note that the ltc2606/ ltc2616/ltc2626 are no more susceptible to these ef- fects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. rail-to-rail output considerations in any rail-to-rail voltage output device, the output is limited to voltages within the supply range. since the analog output of the device cannot go below ground, it may limit for the lowest codes as shown in figure 5b. similarly, limiting can occur near full-scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc as shown in figure 5c. no full-scale limiting can occur if v ref is less than v cc C fse. offset and linearity are de? ned and tested over the region of the dac transfer function where no output limiting can occur.
ltc2606/ltc2616/ltc2626 17 26061626fb operation figure 4. typical ltc2606 input waveformprogramming dac output for full scale ack ack 123456789123456789123456789123456789 2606 f05 ack start x = dont care stop full-scale voltage zero-scale voltage sda a6 a5 a4 a3 a2 a1 a0 scl v out c2 c3 c3 c2 c1 c0 x x x x c1 c0 x x x x ack command d15 d14 d13 d12 d11 d10 d9 d8 ms data d7 d6 d5 d4 d3 d2 d1 d0 ls data a6 a5 a4 a3 a2 a1 a0 wr slave address figure 5. effects of rail-to-rail operation on a dac transfer curve. (a) overall transfer function (b) effect of negative offset for codes near zero scale (c) effect of positive full-scale error for codes near full scale 2606 f05 input code (b) output voltage negative offset 0v 32, 768 0 65, 535 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positive fse
ltc2606/ltc2616/ltc2626 18 26061626fb package description dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev b) 3.00 p 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom viewexposed pad 1.65 p 0.10 (2 sides) 0.75 p 0.05 r = 0.125 typ 2.38 p 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd) dfn rev b 0309 0.25 p 0.05 2.38 p 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 p 0.05 (2 sides) 2.15 p 0.05 0.50 bsc 0.70 p 0.05 3.55 p 0.05 package outline 0.25 p 0.05 0.50 bsc
ltc2606/ltc2616/ltc2626 19 26061626fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 11/09 insert text in serial digital interface section 13 (revision history begins at rev b)
ltc2606/ltc2616/ltc2626 20 26061626fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 1109 rev b ? printed in usa related parts typical application demo circuit schematic. onboard 20-bit adc measures key performance parameters ldac ca0 sda scl ca1 ca2 sck sdo cs f o 9 8 7 10 10 4 2 3 5 1 7 56 2 96 1 2606 ta01 3 100 7.5k 0.1 f 8 v out ca0 ca1 ca2 i 2 c bus v cc ltc2606 gnd 5v v ref 1v to 5v dac output v ref v cc gnd v in ltc2421 fs set zs set 0.1 f spi bus 5v 100pf part number description comments ltc1458/ltc1458l quad 12-bit rail-to-rail output dacs with added functionality ltc1458: v cc = 4.5v to 5.5v, v out = 0v to 4.096v ltc1458l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1654 dual 14-bit rail-to-rail v out dac programmable speed/power, 3.5s/750a, 8s/450a ltc1655/ltc1655l single 16-bit v out dacs with serial interface in so-8 v cc = 5v(3v), low power, deglitched ltc1657/ltc1657l parallel 5v/3v 16-bit v out dacs low power, deglitched, rail-to-rail v out ltc1660/ltc1665 octal 10/8-bit v out dacs in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1821 parallel 16-bit voltage output dac precision 16-bit settling in 2s for 10v step ltc2600/ltc2610 ltc2620 octal 16-/14-/12-bit v out dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2601/ltc2611 ltc2621 single 16-/14-/12-bit v out dacs in 10-lead dfn 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2602/ltc2612 ltc2622 dual 16-/14-/12-bit v out dacs in 8-lead msop 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2604/ltc2614 ltc2624 quad 16-/14-/12-bit v out dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface

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